FIG. 1 shows an example of a DC converter according to a related art. The DC converter shown in FIG. 1 is of an active clamp type disclosed in Japanese Unexamined Patent Application Publication No. 2000-92829. A DC power source Vin is connected through a primary winding P1 (the number of windings of n1) of a transformer T to a main switch Q1 consisting of a MOSFET (hereinafter referred to as FET). Each end of the primary winding P1 is connected to a series circuit consisting of a sub-switch Q2 such as a FET and a snubber capacitor C2. The main switch Q1 and sub-switch Q2 are alternately turned on and off under PWM control by a control circuit 111.
The primary winding P1 of the transformer T and a secondary winding S1 thereof are wound to generate in-phase voltages. The secondary winding S1 (the number of windings of n2) of the transformer T is connected to a rectifying/smoothing circuit consisting of diodes D10 and D11, a reactor L10, and a capacitor C10. The rectifying/smoothing circuit rectifies and smoothes a voltage induced on the secondary winding S1 of the transformer T, i.e., an ON/OFF-controlled pulse voltage and provides a DC output to a load 30.
The control circuit 111 generates, according to the output voltage to the load 30, a control signal composed of pulses to carry out ON/OFF control on the main switch Q1 and controls a duty factor of the control signal to bring the output voltage to a predetermined voltage.
The DC converter further includes an inverter 112, a bottom detection circuit 113, a first delay circuit 114, a second delay circuit 115, a low-side driver 116, and a high-side driver 117.
The inverter 112 inverts a Q1-control signal Q1c for the main switch Q1 provided by the control circuit 111 and outputs the inverted signal to the second delay circuit 115. The bottom detection circuit 113 detects a minimum voltage (bottom voltage) of the main switch Q1 after the sub-switch Q2 is turned off and outputs a bottom detection signal Btm.
The first delay circuit 114 delays the rise timing of the Q1-control signal Q1c from the control circuit 111 up to the fall timing of the bottom detection signal Btm from the bottom detection circuit 113 and provides a Q1-gate signal Q1g to the low-side driver 116. The low-side driver 116 applies the Q1-gate signal Q1g from the first delay circuit 114 to a gate of the main switch Q1, thereby driving the main switch Q1. The second delay circuit 115 delays, by a predetermined time, the rise timing of the Q2-control signal Q2c for the sub-switch Q2 provided by the inverter 112 and provides a Q2-gate signal Q2g to the high-side driver 117. The high-side driver 117 applies the Q2-gate signal Q2g from the second delay circuit 115 to a gate of the sub-switch Q2, thereby driving the sub-switch Q2.
Operation of the DC converter with the above-mentioned structure will be explained with reference to the timing chart of FIG. 2. In FIG. 2, a terminal voltage of the main switch Q1 is depicted by Q1v. 
At time t31, the Q1-control signal Q1c from the control circuit 111 changes to high level, and the Q2-control signal Q2c changes to low level. As a result, the Q2-gate signal Q2g changes to low level to turn off the sub-switch Q2. The bottom detection signal Btm changes to high level at time t31.
When the sub-switch Q2 turns off, the voltage Q1v of the main switch Q1 decreases. At time t32, the bottom detection circuit 113 detects a minimum (bottom) value of the voltage Q1v. At this time, the bottom detection signal Btm from the bottom detection circuit 113 changes to low level.
At the fall timing (time t32) of the bottom detection signal Btm from the bottom detection circuit 113, the Q1-gate signal Q1g generated by the first delay circuit 114 changes to high level. The Q1-gate signal Q1g is applied through the low-side driver 116 to the gate of the main switch Q1, to turn on the main switch Q1. This realizes the bottom voltage switching or zero-volt switching of the main switch Q1.
When the main switch Q1 is turned on, a current from the DC power source Vin is conducted through the primary winding P1 of the transformer T to the main switch Q1. At this time, a current is conducted in the rectifying/smoothing circuit through a route of S1, D10, L10, C10, and S1.
At time t33, the Q1-control signal Q1c turns off the main switch Q1. Then, energy accumulated in the primary winding P1 of the transformer T and in a leakage inductance between the primary and secondary windings of the transformer T charges a parasitic capacitor (not shown) of the main switch Q1, to form a voltage resonance. As a result, the voltage Q1v of the main switch Q1 increases from time t33 to time t34. In the rectifying/smoothing circuit, a current is conducted through a route of L10, C10, D11, and L10 and is supplied to the load 30.
At time t34, the Q2-gate signal Q2g turns on the sub-switch Q2. Then, energy accumulated in the primary winding P1 of the transformer is supplied to the capacitor C2, to charge the capacitor C2. Thereafter, energy accumulated in the capacitor C2 flows through a route of C2, Q2, P1, and C2. The related art is disclosed in Japanese Unexamined Patent Application Publication No. H7-203688, for example.